Verification Engineer

Job Descriptions:

• Understand from design framework definition to RTL-level logic design implementation
• Collaborate with system architects to define the verification architecture and detailed verification specifications based on project requirements
• Apply SystemVerilog language and UVM verification methodology to develop verification platform
• Participate in block level, subsystem level, up to SoC level verification testbench development, maintenance and debug
• Prepare verification plan and derive coverpoints for functional coverage closure
• Perform coverage collection, prepare coverage summary and conduct coverage review
• Collaborate with digital designers to identify potential issue and debug
• Collaborate with analog designers to perform analog-digital co-simulation
• Provide support for testing and validation efforts, including debugging and troubleshooting of controller functionality.

Qualifications:

• Bachelor’s or Master's degree in Electrical / Electronic / Computer Engineering or above, or a related field of experience.
• Proven experience in digital design verification in IC industry.
• Strong expertise in verification methodologies.
• Proficiency in industry-standard EDA tools.
• Familiarity with scripting languages (e.g. Python, Perl, Makefile, etc.) for task automation.
• Exceptional problem-solving and debugging skills.
• Effective communication and teamwork abilities.
• Capacity to work in a collaborative and fast-paced environment.
• Knowledge of protocols and compliance such as UCIe, PCIe or CXL is a plus.
• Experience in ASIC, FPGA and DFT design is a plus.
• Candidates with less experience will be considered for junior positions.